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My ICIP 2006 Schedule
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Paper Detail
| Paper: | WP-P7.4 |
| Session: | Implementation of Image & Video Processing Systems |
| Time: | Wednesday, October 11, 14:20 - 17:00 |
| Presentation: |
Poster |
| Topic: |
Implementation of Image & Video Processing Systems: Hardware and software co-design |
| Title: |
AN FPGA-BASED IMPLEMENTATION OF SPATIO-TEMPORAL OBJECT SEGMENTATION |
| Authors: |
Kumara Ratnayake; Concordia University | | | | | Aishy Amer; Concordia University | | |
| Abstract: |
This paper presents a robust real-time, scalable and modular Field Programmable Gate Array (FPGA) based implementation of a spatio-temporal object segmentation from video signals. The goal of this work is to translate an existing object segmentation algorithm into hardware to achieve real-time performance. The proposed implementation achieved an optimum processing speed of 133 MPixels/s while utilizing minimal hardware resources. The design was successfully simulated, synthesized and tested for real-time performance on an actual hardware platform which consists of a frame grabber with a user programmable FPGA - Xilinx Virtex-II Pro. |
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