ICIP 2006, Atlanta, GA

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Atlanta Conv. & Vis. Bureau


Technical Program

Paper Detail

Session:H.264 Video Coding - II
Time:Tuesday, October 10, 09:40 - 12:20
Presentation: Poster
Authors: Chuan-Yu Cho; National Tsing Hua University 
 Sheng-Kai Chang; National Tsing Hua University 
 Jia-Shung Wang; National Tsing Hua University 
Abstract: The huge computational complexity of motion estimation (ME) process of a standard video codec has resulted in numerous researches on ME VLSI architecture designs. Especially, the new features, variable-block-size (VBS) partitions and multiple-reference-frames (MRF), in the H.264/AVC bring new challenges and opportunities. Though many VLSI designs have been proposed to deal with the new VBS ME feature, there is still no efficient solution for reducing the MRF complexity without drably repeating the whole ME modules. In this paper, an efficient MRF architecture based on a VBS merging scheme is presented. Based on the previous merging scheme, the new architecture can support up to 16 reference frames with the same ME component requirements as a simple 16×16 fixed-block-size ME architecture pluses a few merging logics and five memory latch chains. The proposed architecture is pipelining designed to achieve fully hardware utilization, whereas using the least hardware cost with our previous proposed embedded merging scheme.