ICIP 2006, Atlanta, GA
 

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Paper:WP-P7.12
Session:Implementation of Image & Video Processing Systems
Time:Wednesday, October 11, 14:20 - 17:00
Presentation: Poster
Topic: Implementation of Image & Video Processing Systems: Other
Title: A FAST JPEG2000 EBCOT TIER-1 ARCHITECTURE THAT PRESERVES CODING EFFICIENCY
Authors: Krishnaraj Varma; Virginia Tech 
 Amy Bell; Virginia Tech 
 Hima Damecharla; University of Akron 
 Joan Carletta; University of Akron 
Abstract: Embedded block coding, EBCOT tier-1, is the most computationally intensive part of the JPEG2000 image coding standard. Past research on fast EBCOT tier-1 hardware implementations has concentrated on cycle efficient context formation. These pass-parallel architectures require that JPEG2000's three mode switches be turned on; thus, coding efficiency is sacrificed for improved throughput. In this paper a new fast EBCOT tier-1 design is presented: it is called the Split Arithmetic Encoder (SAE) process. The proposed process exploits concurrency to obtain improved throughput while preserving coding efficiency. The SAE process is evaluated using two methods: clock cycle estimation, and FPGA hardware implementation. Both methods achieve throughput improvement; the hardware implementation exhibits the largest speedup.